As operational requirements increase for electronic structures such as electronic components, e.g., semiconductor chips and modules including same, which mount on PCBs and are coupled together through the board's circuitry, so too must the host PCB be able to compensate for same. One particular increase has been the need for higher frequency connections between the mounted components, which connections, as stated, occur through the underlying host PCB. Such connections are subjected to the detrimental effects, e.g., signal deterioration, caused by the inherent characteristics of such known PCB wiring. For example, signal deterioration is expressed in terms of either the “rise time” or the “fall time” of the signal's response to a step change. The deterioration of the signal can be quantified with the formula (Z0*C)/2, where Z0 is the transmission line characteristic impedance, and C is the amount of the via capacitance. In a wire having a typical 50 ohm transmission line impedance, a plated through hole via having a capacitance of 4 pico farad (pf) would represent a 100 pico-second (ps) rise-time (or fall time) degradation, as compared to a 12.5 ps degradation with a 0.5 pf buried via of the present invention, as discussed below. This difference is significant in systems operation at 800 MHz or faster, where there are associated signal transition rates of 200 ps or faster.
A typical high performance PCB has not been able to provide wiring densities beyond a certain point due to limitations imposed by the direct current (DC) resistance maximum in connections between components (especially chips). Similarly, high speed signals demand wider lines than normal PCB lines to minimize the “skin effect” losses in long lines. To produce a PCB with all wide lines would be impractical, primarily because of the resulting excessive thickness needed for the final board. Such increased thicknesses are obviously unacceptable from a design standpoint.
Various PCBs are described in the following patents:
4,902,610C. Shipley5,336,855J. Kahlert et al5,418,690R. Conn et al5,768,109J. Gulick et al5,891,869S. Lociuro et al5,894,517J. Hutchison et al6,023,211J. Somei6,075,423G. Saunders6,081,430G. La Rue6,146,202S. Ramey et al6,222,740K. Bovensiepen et al6,246,010R. Zenner et al6,431,914T. Billman6,495,772D. Anstrom et alUS2002/0125967R. Garrett et alJP4025155A2O. TakashiThe teachings of these documents are incorporated herein by reference.
As understood from the following, a primary purpose of the present invention is to provide an improved multilayered PCB which provides for enhanced high speed connections between electronic components mounted on the board. By the term “high speed” as used herein is of course meant to mean high frequency.
It is believed that such a board and method of making same would represent a significant advancement in the PCB art.